Since the introduction of synchronous dynamic random access memories (SDRAMs) wherein the data transfer rate of the memory system is directly dependent on system clock rate, a number of advances have been made to further increase the data rate. For example, double data rate (DDR) SDRAMs further increase data transfer rates by causing the data transmission/reception to occur at both rising and falling edges of the system clock. In order to assign a sufficient timing budget in receiving data from a memory controller and a DRAM module with increased data transfer rate, the concept of source synchronous clocking, which allows routing of a synchronous clock through the same path as that of the data, has been introduced. This concept is illustrated in FIGS. 1 and 2.
FIG. 1 illustrates source synchronous clocking using a bidirectional strobe signal DQS as well as the system clock signal CK in a DDR SDRAM. The DQS signals are generated by either a memory controller 20 or DRAM devices 22 and are used as timing reference signals for writing data to the DRAM modules 22 and for reading data from the DRAM modules 22. The data are transferred via the data bus DQ using the DQS strobe signals as a timing reference. The DQS strobe signals are routed through the same path as the DQ signals. The memory controller 20, or DRAM modules 22, sample the data respectively using the strobe signals DQS transmitted through the same path as the data bus, instead of using the system clock CK as a reference. The system clock (CK) is used for sampling the command/address signals (Com/Add) at the DRAM 22, and DQ signals sampled by the DQS signal are translated to the system clock domain internally both at the DRAM 22 and at the controller 20.
FIG. 2 illustrates a typical rambus DRAM configuration. In this configuration, a DRAM module 26 and a memory controller 24 receive two clocks, namely a Clk-From-Master (CFM) signal a Clk-To-Master (CTM) signal. The CFM signal is used as a reference clock for write data, and the CTM signal is used as a reference clock for read data. In each case, the data and clock signals are routed and transferred through the same data path.
For the DDR SDRAM approach illustrated in FIG. 1, a preamble timing interval is required following a read or write command. The preamble interval includes information regarding entry of a valid data strobe signal, and is necessary because the DQS signal can be generated by either the memory controller 20 or the DRAM 22. If the source of the DQS signal changes, then the preamble period must be initiated to pass the token from one to the other. Typically, this preamble interval consumes an entire clock cycle before valid data can be transmitted. Since transmission of data is not permitted during the preamble interval, overall efficiency of the system bus is adversely affected. In the rambus DRAM approach illustrated in FIG. 2, the use of the forward clock CFM and the return clock CTM again results in the crossing of two clock domains within a DRAM module 26. The resulting configuration is therefore complicated since sophisticated compensation circuitry is required to manage the phase difference between the CFM and CTM clock signals, and since an initialization procedure is needed for the phase compensation circuitry. In both DDR SDRAM and rambus DRAM architectures, the pin count for the memory module connector is increased due to the increased number of clock pins, and in the case of rambus, the data pin count is doubled.